The fabrication of modern circuits typically involves several steps. Integrated circuits are first fabricated on a semiconductor wafer, which contains multiple duplicated semiconductor chips, each comprising integrated circuits. The semiconductor chips are then sawed from the wafer and packaged. The packaging processes have two main purposes: to protect delicate semiconductor chips, and to connect interior integrated circuits to exterior pins.
In conventional packaging processes, a semiconductor chip may be mounted on a package component using flip-chip bonding. An Underfill is dispensed into the gap between the semiconductor chip and the package component to prevent cracks from being formed in solder bumps or solder balls, wherein cracks are typically caused by thermal stresses. The package component may be an interposer that includes metal connections for routing electrical signals between opposite sides. The chip may be bonded to the interposer through direct metal bonding, solder bonding, or the like.
With the increasing demand for more functions, system-in-package (SiP) technology, in which two or more chips are packaged on one module substrate, has increasingly been used. Furthermore, package-on-package (PoP) technology is also used to further expand the integration ability of the packages. When the PoP technology is used, packages are stacked. With a high degree of integration, the electrical performance of the resulting package is improved due to the shortened connecting path between components. By using SiP and/or PoP technologies, package design becomes more flexible and less complex. Time-to-market is also reduced for product upgrades.
With the increase in the size of the package, greater stresses are introduced. Furthermore, the non-uniformity in the stress distribution inside packages becomes more severe. Due to the greater stresses in local regions, packages are more prone to failures. Possible failures in a package include bump cracking, substrate cracking, low-k material or underfill delaminating, BGA ball cracking, etc. Efforts have been taken to solve these problems by using interposers based on organic substrates, which are formed of fiber-filled cores and build-up layers. The use of the interposers that have organic substrates, however, still cannot eliminate some of the problems since the coefficients of thermal expansion (CTEs) of the organic substrates are significantly higher than the CTE of silicon substrates. On the other hand, although the silicon substrates in the interposers have the same CTE as the CTE of the substrates in the device dies, the manufacturing cost of the interposers based on the silicon substrates is high.